MC9S12HY64 Datasheet, PDF (135/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Chapter 3 S12P Memory Map Control (S12PMMCV1)
Table 3-1. Revision History Table
Rev. No.
Date
(Item No.) (Submitted By)
Sections
Affected
Substantial Change(s)
01.03
01.04
01.04
18.APR.2008
27.Jun.2008
11.Jul.2008
Section 3.3.2.3,
“Program Page
Index Register
Corrected the address offset of the PPAGE register (on page 3-140)
(PPAGE)”
Section 3.5.1,
“Implemented Removed “Table 1-9. MC9S12P Derivatives”
Memory Map”
Removed references to the MMCCTL1 register
3.1 Introduction
The S12PMMC module controls the access to all internal memories and peripherals for the CPU12 and
S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip
ressources. Figure 3-1 shows a block diagram of the S12PMMC module.
3.1.1 Glossary
Table 3-2. Glossary Of Terms
Term
Definition
Local Addresses
Address within the CPU12’s Local Address Map (Figure 3-10)
Global Addresse
Address within the Global Address Map (Figure 3-10)
Aligned Bus Access
Bus access to an even address.
Misaligned Bus Access
Bus access to an odd address.
NS
Normal Single-Chip Mode
SS
Special Single-Chip Mode
Unimplemented Address Ranges _{Address ranges which are not mapped to any on-chip ressource.}
P-Flash
Program Flash
D-Plash
Data Flash
NVM
Non-volatile Memory; P-Flash or D-Flash
IFR
NVM Information Row. Refer to FTMRC Block Guide
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
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