MC9S12HY64 Datasheet, PDF (629/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

64 KByte Flash Module (S12FTMRC64K1V1)
Table 17-15. FERSTAT Field Descriptions
Field
Description
1
DFDIF
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was
detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation
was attempted on a Flash block that was under a Flash command operation.¹ The DFDIF flag is cleared by
writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
0 No double bit fault detected
1 Double bit fault detected or an invalid Flash array read operation attempted
0
SFDIF
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation.¹
The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or an invalid Flash array read operation attempted
1 _{The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either}
single fault or double fault but never both). A simultaneous access collision (read attempted while command running) is
indicated when both SFDIF and DFDIF flags are high.
17.3.2.9 P-Flash Protection Register (FPROT)
The FPROT register defines which P-Flash sectors are protected against program and erase operations.
Offset Module Base + 0x0008
7
R
FPOPEN
W
6
RNV6
5
FPHDIS
4
3
FPHS[1:0]
2
FPLDIS
Reset
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 17-13. Flash Protection Register (FPROT)
1
0
FPLS[1:0]
F
F
The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected
region can only be increased (see Section 17.3.2.9.1, “P-Flash Protection Restrictions,” and Table 17-20).
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte
in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see Table 17-3)
as indicated by reset condition ‘F’ in Figure 17-13. To change the P-Flash protection that will be loaded
during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash
protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase
containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and
remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.
Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible
if any of the P-Flash sectors contained in the same P-Flash block are protected.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
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