MC9S12HY64 Datasheet, PDF (225/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Chapter 7
S12 Clock, Reset and Power Management Unit (S12CPMU)
Block Description
Revision History
Version Revision Effective
Number Date
Date
V01.00 16 Jan.07 16 Jan. 07
V01.01 9 July 08 9 July 08
V01.02 7 Oct. 08 7 Oct. 08
V01.03 11 Dec. 08 11 Dec. 08
V01.04 17 Jun. 09 17 Jun. 09
V01.05 27 Apr. 10 27 Apr. 10
Author
Description of Changes
Initial release
added IRCLK to Block Diagram
clarified and detailed oscillator filter functionality
added note, that startup time of external oscillator t_UPOSC must be
considered, especially when entering Pseudo Stop Mode
Modified reset phase descriptions to reference f_VCORST instead of
f_PLLRST and correct typo of RESET pin sample point from 64 to 256
cycles in section: Description of Reset Operation
Major rework fixing typos, figures and tables and improved
description of Adaptive Oscillator Filter.
7.1 Introduction
This specification describes the function of the Clock, Reset and Power Management Unit (S12CPMU).
• The Pierce oscillator (OSCLCP) provides a robust, low-noise and low-power external clock source.
It is designed for optimal start-up margin with typical crystal oscillators.
• The Voltage regulator (IVREG) operates from the range 3.13V to 5.5V. It provides all the required
chip internal voltages and voltage monitors.
• The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter.
• The Internal Reference Clock (IRC1M) provides a1MHz clock.
7.1.1 Features
The Pierce Oscillator (OSCLCP) contains circuitry to dynamically control current gain in the output
amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
225