MC9S12HY64 Datasheet, PDF (429/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Serial Communication Interface (S12SCIV5)
12.3.2.3 SCI Alternative Status Register 1 (SCIASR1)
Module Base + 0x0000
7
6
5
4
R
0
0
0
RXEDGIF
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
2
0
BERRV
0
0
Figure 12-6. SCI Alternative Status Register 1 (SCIASR1)
1
BERRIF
0
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Table 12-6. SCIASR1 Field Descriptions
0
BKDIF
0
Field
Description
7
RXEDGIF
Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0,
rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.
0 No active receive on the receive input has occurred
1 An active edge on the receive input has occurred
2
BERRV
Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and
a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.
0 A low input was sampled, when a high was expected
1 A high input reassembled, when a low was expected
1
BERRIF
Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value
sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an
interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.
0 No mismatch detected
1 A mismatch has occurred
0
BKDIF
Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is
received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing
a “1” to it.
0 No break signal was received
1 A break signal was received
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
429