MC9S12HY64 Datasheet, PDF(279/792 Page) Freescale Semiconductor, Inc – S12 Microcontrollers

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MC9S12HY64 Datasheet, PDF (279/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

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S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description

7.6.1.4 Low-Voltage Interrupt (LVI)

In FPM the input voltage VDDA is monitored. Whenever VDDA drops below level VLVIA, the status bit

LVDS is set to 1. On the other hand, LVDS is reset to 0 when VDDA rises above level VLVID. An interrupt,

indicated by ï¬ag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE

= 1.

7.6.1.5 HTI - High Temperature Interrupt

In FPM the junction temperature TJ is monitored. Whenever TJ exceeds level THTIA the status bit HTDS

is set to 1. Vice versa, HTDS is reset to 0 when TJ get below level THTID. An interrupt, indicated by ï¬ag

HTIF = 1, is triggered by any change of the status bit HTDS, if interrupt enable bit HTIE = 1.

7.6.1.6 Autonomous Periodical Interrupt (API)

The API sub-block can generate periodical interrupts independent of the clock source of the MCU. To

enable the timer, the bit APIFE needs to be set.

The API timer is either clocked by a trimmable internal RC oscillator (ACLK) or the Bus Clock. Timer

operation will freeze when MCU clock source is selected and Bus Clock is turned off. The clock source

can be selected with bit APICLK. APICLK can only be written when APIFE is not set.

The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is

cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When

the conï¬gured time has elapsed, the ï¬ag APIF is set. An interrupt, indicated by ï¬ag APIF = 1, is triggered

if interrupt enable bit APIE = 1. The timer is re-started automatically again after it has set APIF.

The procedure to change APICLK or APIR[15:0] is ï¬rst to clear APIFE, then write to APICLK or

APIR[15:0], and afterwards set APIFE.

The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency

is desired.

See Table 7-17 for the trimming effect of APITR.

NOTE

The ï¬rst period after enabling the counter by APIFE might be reduced by

API start up delay tsdel.

It is possible to generate with the API a waveform at the external pin API_EXTCLK by setting APIFE and

enabling the external access with setting APIEA.

7.7 Initialization/Application Information

MC9S12HY/HA-Family Reference Manual, Rev. 1.04

Freescale Semiconductor

279

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