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MC9S12HY64 Datasheet, PDF (333/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
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Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Table 9-26. Message Buffer Organization
Offset
Address
Register
0x00X0 Identiï¬er Register 0
0x00X1 Identiï¬er Register 1
0x00X2 Identiï¬er Register 2
0x00X3 Identiï¬er Register 3
0x00X4 Data Segment Register 0
0x00X5 Data Segment Register 1
0x00X6 Data Segment Register 2
0x00X7 Data Segment Register 3
0x00X8 Data Segment Register 4
0x00X9 Data Segment Register 5
0x00XA Data Segment Register 6
0x00XB Data Segment Register 7
0x00XC
0x00XD
Data Length Register
Transmit Buffer Priority Register(1)
0x00XE Time Stamp Register (High Byte)
0x00XF Time Stamp Register (Low Byte)
1. Not applicable for receive buffers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Figure 9-24 shows the common 13-byte data structure of receive and transmit buffers for extended
identiï¬ers. The mapping of standard identiï¬ers into the IDR registers is shown in Figure 9-25.
All bits of the receive and transmit buffers are âxâ out of reset because of RAM-based implementation1.
All reserved or unused bits of the receive and transmit buffers always read âxâ.
1. Exception: The transmit buffer priority registers are 0 out of reset.
MC9S12HY/HA-Family Reference Manual Rev. 1.04
Freescale Semiconductor
333
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