MC9S12HY64 Datasheet, PDF (273/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

7.4.6
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
System Clock Configurations
7.4.6.1 PLL Engaged Internal Mode (PEI)
This mode is the default mode after System Reset or Power-On Reset.
The Bus Clock is based on the PLLCLK, the reference clock for the PLL is internally generated (IRC1M).
The PLL is configured to 64 MHz VCOCLK with POSTDIV set to 0x03. If locked (LOCK=1) this results
in a PLLCLK of 16 MHz and a Bus Clock of 8 MHz. The PLL can be re-configured to other bus
frequencies.
The clock sources for COP and RTI are based on the internal reference clock generator (IRC1M).
7.4.6.2 PLL Engaged External Mode (PEE)
In this mode, the Bus Clock is based on the PLLCLK as well (like PEI). The reference clock for the PLL
is based on the external oscillator. The adaptive spike filter and detection logic which uses the VCOCLK
to filter and qualify the external oscillator clock can be enabled.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock.
This mode can be entered from default mode PEI by performing the following steps:
1. Configure the PLL for desired bus frequency.
2. Optionally the adaptive spike filter and detection logic can be enabled by calculating the integer
value for the OSCFIL[4:0] bits and setting the bandwidth (OSCBW) accordingly.
3. Enable the external oscillator (OSCE bit).
4. Wait for the PLL being locked (LOCK = 1) and the oscillator to start-up and additionally being
qualified if the adaptive spike filter is enabled (UPOSC =1).
5. Clear all flags in the CPMUFLG register to be able to detect any future status bit change.
6. Optionally status interrupts can be enabled (CPMUINT register).
Since the adaptive spike filter (filter and detection logic) uses the VCOCLK to continuously filter and
qualify the external oscillator clock, loosing PLL lock status (LOCK=0) means loosing the oscillator status
information as well (UPOSC=0).
The impact of loosing the oscillator status in PEE mode is as follows:
• The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
273