MC9S12HY64 Datasheet, PDF (288/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Analog-to-Digital Converter (ADC12B8CV1) Block Description
1_{If only AN0 should be converted use MULT=0.}
8.3.2.2 ATD Control Register 1 (ATDCTL1)
Writes to this register will abort current conversion sequence.
Module Base + 0x0001
7
R
ETRIGSEL
W
Reset
0
6
SRES1
5
SRES0
4
3
2
1
0
SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
0
1
0
1
1
1
1
Figure 8-4. ATD Control Register 1 (ATDCTL1)
Read: Anytime
Write: Anytime
Table 8-3. ATDCTL1 Field Descriptions
Field
Description
7
ETRIGSEL
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-0
inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
not effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in Table 8-5.
6–5
A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 8-4 for coding.
SRES[1:0]
4
SMP_DIS
Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
3–0
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 8-5.
Table 8-4. A/D Resolution Coding
SRES1
0
0
1
1
SRES0
0
1
0
1
A/D Resolution
8-bit data
10-bit data
12-bit data
Reserved
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
288
Freescale Semiconductor