MC9S12HY64 Datasheet, PDF (335/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Figure 9-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued)
Register
Name
Bit 7
6
5
4
3
2
1
Bit0
= Unused, always read ‘x’
Read:
• For transmit buffers, anytime when TXEx flag is set (see Section 9.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 9.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
• For receive buffers, only when RXF flag is set (see Section 9.3.2.5, “MSCAN Receiver Flag
Register (CANRFLG)”).
Write:
• For transmit buffers, anytime when TXEx flag is set (see Section 9.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 9.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
• Unimplemented for receive buffers.
Reset: Undefined because of RAM-based implementation
Register
Name
IDR0
0x00X0
Figure 9-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
Bit 7
6
5
4
3
2
1
R
ID10
ID9
ID8
ID7
ID6
ID5
ID4
W
Bit 0
ID3
IDR1
R
0x00X1 _W
ID2
ID1
ID0
RTR
IDE (=0)
IDR2
R
0x00X2 _W
IDR3
R
0x00X3 _W
= Unused, always read ‘x’
9.3.3.1 Identifier Registers (IDR0–IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE,
and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0],
RTR, and IDE bits.
MC9S12HY/HA-Family Reference Manual Rev. 1.04
Freescale Semiconductor
335