MC9S12HY64 Datasheet, PDF (74/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12HYPIMV1)
Table 2-7. DDRB Register Field Descriptions
Field
7-0
DDRB
Description
Port B Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
1 Associated pin is configured as output
0 Associated pin is configured as input
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTA, PTB registers, when changing the
DDRA,DDRB register.
2.3.7 PIM Reserved Register
Address 0x0004 (PRR) to 0x0007 (PRR)
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-5. PIM Reserved Register
Access: User read¹
1
0
0
0
0
0
2.3.8 Ports A, B, BKGD pin Pull Control Register (PUCR)
Address 0x000C (PRR)
Access: User read/write¹
7
6
5
4
3
2
1
R
0
0
0
0
0
BKPUE
PUPBE
W
Reset
0
1
0
0
0
0
1
= Unimplemented or Reserved
Figure 2-6. Ports AB, BKGD pin Pull Control Register (PUCR)
1 _{Read:Anytime in single-chip modes.}
Write:Anytime, except BKPUE which is writable in Special Single-Chip Mode only.
0
PUPAE
1
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
74
Freescale Semiconductor