MC9S12HY64 Datasheet, PDF (476/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Serial Peripheral Interface (S12SPIV5)
End of Idle State
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
Begin
Transfer
End
Begin of Idle State
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
t_L
MSB first (LSBFE = 0): MSB
LSB first (LSBFE = 1): LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
t_L = Minimum leading time before the first SCK edge
t_T = Minimum trailing time after the last SCK edge
t_I = Minimum idling time between transfers (minimum SS high time)
t_L, t_T, and t_I are guaranteed for the master mode and required for the slave mode.
Bit 1
Bit 6
t_T t_I t_L
LSB Minimum 1/2 SCK
MSB
for t_T, t_l, t_L
Figure 13-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
476
Freescale Semiconductor