MC9S12HY64 Datasheet, PDF (118/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12HYPIMV1)
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTU or PTIU registers, when changing the
DDRU register.
2.3.76 PIM Reserved Registers
Address 0x0293
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-74. PIM Reserved Registers
Access: User read¹
1
0
0
0
0
0
2.3.77 Port U Pull Device Enable Register (PERU)
Address 0x0294
R
W
Reset
7
PERU7
0
1 _{Read: Anytime.}
Write: Anytime.
6
PERU6
5
PERU5
4
PERU4
3
PERU3
2
PERU2
0
0
0
0
0
Figure 2-75. Port U Pull Device Enable Register (PERU)
Access: User read/write¹
1
0
PERU1
PERU0
0
0
Table 2-65. PERU Register Field Descriptions
Field
7-0
PERU
Description
Port U pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
118
Freescale Semiconductor