MC9S12HY64 Datasheet, PDF (190/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12S Debug Module (S12SDBGV2)
6.3.2.3 Debug Trace Control Register (DBGTCR)
Address: 0x0022
7
6
5
4
3
2
1
0
R
0
0
0
TSOURCE
W
TRCMOD
0
TALIGN
Reset
0
0
0
0
0
0
0
0
Figure 6-5. Debug Trace Control Register (DBGTCR)
Read: Anytime
Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed.
Table 6-7. DBGTCR Field Descriptions
Field
Description
6
TSOURCE
Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU
system is secured, this bit cannot be set and tracing is inhibited.
This bit must be set to read the trace buffer.
0 Debug session without tracing requested
1 Debug session with tracing requested
3–2
TRCMOD
Trace Mode Bits — See 6.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of flow
information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace
memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. In
Compressed Pure PC mode the program counter value for each instruction executed is stored. See Table 6-8.
0
TALIGN
Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session.
0 Trigger at end of stored data
1 Trigger before storing data
TRCMOD
00
01
10
11
Table 6-8. TRCMOD Trace Mode Bit Encoding
Description
Normal
Loop1
Detail
Compressed Pure PC
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
190
Freescale Semiconductor