MC9S12HY64 Datasheet, PDF (221/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12S Debug Module (S12SDBGV2)
6.5.4 Scenario 3
A trigger is generated immediately when one of up to 3 given events occurs
Figure 6-31. Scenario 3
SCR1=0000
State1
M012 _{Final State}
Scenario 3 is possible with S12SDBGV1 SCR encoding
6.5.5 Scenario 4
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B
and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate
event B cause a trigger. Similarly 2 consecutive occurrences of event B without an intermediate event A
cause a trigger. This is possible by using CompA and CompC to match on the same address as shown.
Figure 6-32. Scenario 4a
SCR1=0100 _State1
M0
State2 ^SCR2=0011
M1
M2
M0
M1
SCR3=0001 ^{State 3}
Final State
M1
This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2
comparators, State 3 allowing a M0 to return to state 2, whilst a M2 leads to final state as shown.
Figure 6-33. Scenario 4b (with 2 comparators)
SCR1=0110 _State1
M0
State2 ^SCR2=1100
M2
SCR3=1110 ^{State 3}
M0
M2
M2
M01
Final State
M1 disabled in
range mode
The advantage of using only 2 channels is that now range comparisons can be included (channel0)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
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