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MC9S12HY64 Datasheet, PDF (136/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
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S12P Memory Map Control (S12PMMCV1)
3.1.2 Overview
The S12PMMC connects the CPU12âs and the S12SBDMâs bus interfaces to the MCUâs on-chip
ressources (memories and peripherals). It arbitrates the bus accesses and detemines all of the MCUâs
memory maps. Furthermore, the S12PMMC is responsible for constraining memory accesses on secured
devices and for selecting the MCUâs functional mode.
3.1.3 Features
The main features of this block are:
⢠Paging capability to support a global 256 KByte memory address space
⢠Bus arbitration between the masters CPU12, S12SBDM to different resources.
⢠MCU operation mode control
⢠MCU security control
⢠Separate memory map schemes for each master CPU12, S12SBDM
⢠Generation of system reset when CPU12 accesses an unimplemented address (i.e., an address
which does not belong to any of the on-chip modules) in single-chip modes
3.1.4 Modes of Operation
The S12PMMC selects the MCUâs functional mode. It also determines the devices behavior in secured and
unsecured state.
3.1.4.1 Functional Modes
Two funtional modes are implementes on devices of the S12P product family:
⢠Normal Single Chip (NS)
The mode used for running applications.
⢠Special Single Chip Mode (SS)
A debug mode which causes the device to enter BDM Active Mode after each reset. Peripherals
may also provide special debug features in this mode.
3.1.4.2 Security
S12P devives can be secured to prohibit external access to the on-chip P-Flash. The S12PMMC module
determines the access permissions to the on-chip memories in secured and unsecured state.
3.1.5 Block Diagram
Figure 3-1 shows a block diagram of the S12PMMC.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
136
Freescale Semiconductor
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