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MC9S12HY64 Datasheet, PDF (709/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers
Motor Controller (MC10B8CV1)
19.4.2 PWM Duty Cycle
The PWM duty cycle for the motor controller channel x can be determined by dividing the decimal
representation of bits D[10:0] in MCDCx by the decimal representation of the bits P[10:0] in MCPER and
multiplying the result by 100% as shown in the equation below:
Effective PWM Channel X % Duty Cycle = M---D---C-U----P-T--E--Y--R--- ⋅ 100%
NOTE
x = PWM Channel Number = 0, 1, 2, 3 ... 8. This equation is only valid if
DUTY <= MCPER and MCPER is not equal to 0.
Whenever D[10:0] >= P[10:0], a constant low level (RECIRC = 0) or high level (RECIRC = 1) will be
output.
19.4.3 Motor Controller Counter Clock Source
Figure 19-22 shows how the PWM motor controller timer counter clock source is selected.
Clock
Generator
CLK
Peripheral
Bus
Clock fBUS
Clocks and
Reset
Generator
Module
Motor Controller
Timer
Counter Clock
Prescaler Select
MPPRE0, MPPRE1
1
1/2
Motor Controller Timer
1/4
1/8
Counter Clock fTC
Motor Controller Timer
Counter Prescaler
11-Bit Motor Controller
Timer Counter
Figure 19-22. Motor Controller Counter Clock Selection
The peripheral bus clock is the source for the motor controller counter prescaler. The motor controller
counter clock rate, fTC, is set by selecting the appropriate prescaler value. The prescaler is selected with
the MCPRE[1:0] bits in motor controller control register 0 (MCCTL0). The motor controller channel
frequency of operation can be calculated using the following formula if DITH = 0:
Motor Channel Frequency (Hz) = M------C-----P--f-E-T--C-R------⋅---M----
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
709