MC9S12HY64 Datasheet, PDF (277/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to
the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out
period. A premature write will immediately reset the part.
7.5.3 Power-On Reset (POR)
The on-chip POR circuitry detects when the internal supply V_DD drops below an appropriate voltage level
(voltage level not specified in this document because this supply is not visible on device pins). POR is
deasserted, if the internal supply V_DD exceeds an appropriate voltage level (voltage level not specified in
this document because this supply is not visible on device pins).
7.5.4 Low-Voltage Reset (LVR)
The on-chip LVR circuitry detects when one of the supply voltages V_DD, V_DDF or V_DDX drops below an
appropriate voltage level. If LVR is deasserted the MCU is fully operational at the specified maximum
speed.The LVR assert and deassert levels for the supply voltage VDDX are V_LVRXA and V_LVRXD and are
specified in the device Reference Manual.
7.6 Interrupts
The interrupt/reset vectors requested by the S12CPMU are listed in Table 7-27. Refer to MCU
specification for related vector addresses and priorities.
Table 7-27. S12CPMU Interrupt Vectors
Interrupt Source
CCR
Mask
Local Enable
RTI time-out interrupt
I bit
CPMUINT (RTIE)
PLL lock interrupt
I bit
CPMUINT (LOCKIE)
Oscillator status
I bit
interrupt
CPMUINT (OSCIE)
Low voltage interrupt
I bit
High temperature
interrupt
I bit
Autonomous
Periodical Interrupt
I bit
CPMULVCTL (LVIE)
CPMUHTCTL (HTIE)
CPMUAPICTL (APIE)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
277