MC9S12HY64 Datasheet, PDF (622/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

64 KByte Flash Module (S12FTMRC64K1V1)
Address
& Name
7
6
5
4
3
2
1
0
0x0011
R
0
0
0
0
0
0
0
0
FRSV5 _W
0x0012
R
0
0
0
0
0
0
0
0
FRSV6 _W
0x0013
R
0
0
0
0
0
0
0
0
FRSV7 _W
= Unimplemented or Reserved
Figure 17-4. FTMRC64K1 Register Summary (continued)
17.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R FDIVLD
W
FDIVLCK
FDIV[5:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 17-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field.
CAUTION
The FCLKDIV register must never be written to while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
Table 17-6. FCLKDIV Field Descriptions
Field
7
FDIVLD
Description
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
622
Freescale Semiconductor