MC9S12HY64 Datasheet, PDF (511/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Timer Module (TIM16B8CV2) Block Description
NOTE
The pulse accumulator counter can operate in event counter mode even
when the timer enable bit, TEN, is clear.
14.4.6 Gated Time Accumulation Mode
Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation. An active
level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE
bit selects low levels or high levels to enable the divided-by-64 clock.
The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF flag to
generate interrupt requests.
The pulse accumulator counter register reflect the number of pulses from the divided-by-64 clock since the
last reset.
NOTE
The timer prescaler generates the divided-by-64 clock. If the timer is not
active, there is no divided-by-64 clock.
14.5 Resets
The reset state of each individual bit is listed within Section 14.3, “Memory Map and Register Definition”
which details the registers and their bit fields.
14.6 Interrupts
This section describes interrupts originated by the TIM16B8CV2 block. Table 14-25 lists the interrupts
generated by the TIM16B8CV2 to communicate with the MCU.
Table 14-25. TIM16B8CV1 Interrupts
Interrupt
Offset¹ Vector¹ Priority¹
Source
Description
C[7:0]F
—
—
PAOVI
—
—
PAOVF
—
—
TOF
—
—
1 _{Chip Dependent.}
—
Timer Channel 7–0
Active high timer channel interrupts 7–0
—
Pulse Accumulator Active high pulse accumulator input interrupt
Input
—
Pulse Accumulator
Overflow
Pulse accumulator overflow interrupt
—
Timer Overflow
Timer Overflow interrupt
The TIM16B8CV2 uses a total of 11 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.
MC9S12HY/HA-Family Reference Manual Rev. 1.04
Freescale Semiconductor
511