MC9S12HY64 Datasheet, PDF (214/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12S Debug Module (S12SDBGV2)
each trace buffer entry. In Detail mode CINF comprises of R/W and size access information (CRW and
CSZ respectively).
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (DATAL)
and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to
trace buffer byte1 and the byte at the higher address is stored to byte0.
Mode
Table 6-37. Trace Buffer Organization (Normal,Loop1,Detail modes)
Entry
Number
4-bits
Field 2
8-bits
Field 1
8-bits
Field 0
Detail Mode
Entry 1
Entry 2
CINF1,ADRH1
0
CINF2,ADRH2
0
ADRM1
DATAH1
ADRM2
DATAH2
ADRL1
DATAL1
ADRL2
DATAL2
Normal/Loop1 ^{Entry 1}
Modes
Entry 2
PCH1
PCH2
PCM1
PCM2
PCL1
PCL2
6.4.5.3.1 Information Bit Organization
The format of the bits is dependent upon the active trace mode as described below.
Field2 Bits in Detail Mode
Bit 3
Bit 2
Bit 1
Bit 0
CSZ
CRW ADDR[17] ADDR[16]
Figure 6-25. Field2 Bits in Detail Mode
In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU.
Table 6-38. Field Descriptions
Bit
Description
3
CSZ
Access Type Indicator— This bit indicates if the access was a byte or word size when tracing in Detail Mode
0 Word Access
1 Byte Access
2
CRW
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access when tracing in Detail Mode.
0 Write Access
1 Read Access
1
Address Bus bit 17— Corresponds to system address bus bit 17.
ADDR[17]
0
Address Bus bit 16— Corresponds to system address bus bit 16.
ADDR[16]
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
214
Freescale Semiconductor