MC9S12HY64 Datasheet, PDF (272/792 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
The use of the filter function is only possible if the VCOCLK-to-OSCCLK ratio divided by two ((f_VCO /
f_OSC)/2) is an integer number. This integer value must be written to the OSCFILT[4:0] bits.
If enabled, the oscillator filter is sampling the incoming oscillator clock signal (EXTAL) with the
VCOCLK frequency.
Using VCOCLK, a time window is defined during which an edge of the OSCCLK is expected. In case of
OSCBW = 1 the width of this window is three VCOCLK cycles, if the OSCBW = 0 it is one VCOCLK
cycle.
The noise detection is active for certain combinations of OSCFILT[4:0] and OSCBW bit settings as shown
in Table 7-24
Table 7-24. Noise Detection Settings
OSCFILT[4:0]
0
1
2 or 3
>=4
OSCBW
x
x
0
1
x
Detection
disabled
disabled
active
disabled
active
Filter
disabled
active
active
active
active
NOTE
If the VCOCLK frequency is higher than 25 MHz the wide bandwidth must
be selected (OSCBW = 1).
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
272
Freescale Semiconductor