LM3S3748 Datasheet, PDF (75/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
6.3 Register Map
Table 6-1 on page 75 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
Note: Additional Flash and ROM registers defined in the System Control register space are
described in the “Internal Memory” on page 160.
Table 6-1. System Control Register Map
Offset Name
Type
Reset
Description
0x000 DID0
0x004 DID1
0x008 DC0
0x010 DC1
0x014 DC2
0x018 DC3
0x01C DC4
0x020 DC5
0x024 DC6
0x028 DC7
0x030 PBORCTL
0x034 LDOPCTL
0x040 SRCR0
0x044 SRCR1
0x048 SRCR2
0x050 RIS
0x054 IMC
0x058 MISC
0x05C RESC
0x060 RCC
0x064 PLLCFG
0x06C GPIOHSCTL
0x070 RCC2
0x07C MOSCCTL
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W1C
R/W
R/W
RO
R/W
R/W
R/W
-
-
0x00FF.003F
0x0011.33FF
0x030F.5133
0xBFFF.86FF
0x0000.F0FF
0x0F30.00FF
0x0000.0002
0x03C0.0F3F
0x0000.7FFD
0x0000.0000
0x00000000
0x00000000
0x00000000
0x0000.0000
0x0000.0000
0x0000.0000
-
0x078E.3AD1
-
0x0000.0000
0x0780.6810
0x0000.0000
Device Identification 0
Device Identification 1
Device Capabilities 0
Device Capabilities 1
Device Capabilities 2
Device Capabilities 3
Device Capabilities 4
Device Capabilities 5
Device Capabilities 6
Device Capabilities 7
Brown-Out Reset Control
LDO Power Control
Software Reset Control 0
Software Reset Control 1
Software Reset Control 2
Raw Interrupt Status
Interrupt Mask Control
Masked Interrupt Status and Clear
Reset Cause
Run-Mode Clock Configuration
XTAL to PLL Translation
GPIO High Speed Control
Run-Mode Clock Configuration 2
Main Oscillator Control
See
page
77
97
99
100
102
104
106
107
109
110
79
80
133
134
136
81
82
83
84
85
90
91
93
95
April 08, 2008
75
Preliminary