LM3S3748 Datasheet, PDF (565/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Bit/Field
4
3
2
1
0
Name
FLUSH
DATAERR
OVER
FULL
RXRDY
Type
W1S
RO
R/W0C
RO
R/W0C
Reset
0
0
0
0
0
Description
Flush FIFO
The CPU writes a 1 to this bit to flush the next packet to be read from
the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit
is cleared.
Note:
The FLUSH bit should only be used when RXRDY is set. At
other times, it may cause data to be corrupted. Also note that,
if the FIFO is double-buffered, FLUSH may need to be set
twice to completely clear the FIFO.
Data Error
This bit is set when RXRDY is set if the data packet has a CRC or bit-stuff
error. It is cleared when RXRDY is cleared.
Note: This bit is only valid when the endpoint is operating in ISO
mode. In Bulk mode, it always returns zero.
Overrun
This bit is set if an OUT packet cannot be loaded into the receive FIFO.
The CPU should clear this bit.
Note: This bit is only valid when the endpoint is operating in ISO
mode. In Bulk mode, it always returns zero.
FIFO Full
This bit is set when no more packets can be loaded into the receive
FIFO.
Receive Packet Ready
This bit is set when a data packet has been received. The CPU should
clear this bit when the packet has been unloaded from the receive FIFO.
An interrupt is generated when the bit is set.
April 08, 2008
565
Preliminary