LM3S3748 Datasheet, PDF (59/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
5.2.4.1
GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting
GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate
hardware function (setting GPIOAFSEL to 1) for the PC[3:0] JTAG/SWD pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PC[3:0] in
the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or
board-level testing, this provides four more GPIOs for use in the design.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris^® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 269), GPIO Pull-Up Select (GPIOPUR) register (see page 275), and GPIO Digital
Enable (GPIODEN) register (see page 278) are not committed to storage unless the GPIO Lock
(GPIOLOCK) register (see page 280) has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register (see page 281) have been set to 1.
Recovering a "Locked" Device
Note:
Performing the below sequence will cause the nonvolatile registers discussed in “Nonvolatile
Register Programming” on page 163 to be restored to their factory default values. The mass
erase of the flash memory caused by the below sequence occurs prior to the nonvolatile
registers being restored.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the device. Performing
a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset
mass erases the flash memory. The sequence to recover the device is:
1. Assert and hold the RST signal.
2. Perform the JTAG-to-SWD switch sequence.
3. Perform the SWD-to-JTAG switch sequence.
4. Perform the JTAG-to-SWD switch sequence.
5. Perform the SWD-to-JTAG switch sequence.
6. Perform the JTAG-to-SWD switch sequence.
7. Perform the SWD-to-JTAG switch sequence.
8. Perform the JTAG-to-SWD switch sequence.
9. Perform the SWD-to-JTAG switch sequence.
10. Perform the JTAG-to-SWD switch sequence.
April 08, 2008
59
Preliminary