LM3S3748 Datasheet, PDF (568/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
Bit/Field
2
1
0
Name
DTWE
DT
INCRX
Type
RO
RO
R/W0C
Reset
0
0
0
Description
Data Toggle Write Enable
The CPU writes a 1 to this bit to enable the current state of the endpoint
0 data toggle to be written (see DT). This bit is automatically cleared
once the new value is written.
Data Toggle
When read, this bit indicates the current state of the endpoint 0 data
toggle. If DTWE is High, this bit may be written with the required setting
of the data toggle. If DTWE is Low, any value written to this bit is ignored.
Incomplete Receive
This bit is set in a high-bandwidth isochronous or interrupt transfer if the
packet received is incomplete. It is cleared when RXRDY is cleared.
Note:
If USB protocols are followed correctly, this bit should never
be set. The bit becoming set indicates a failure of the
associated peripheral device to behave correctly. (In anything
other than isochronous transfer, this bit always returns 0.)
USBRXCSRHn Device Mode
USB Receive Control and Status Endpoint 1 High (USBRXCSRH1)
Base 0x4005.0000
Offset 0x117
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
AUTOCL ISO DMAEN DISNYET/PIDERR DMAMOD
reserved
INCRX
Type R/W
R/W
R/W
R/W
R/W
RO
Reset
0
0
0
0
0
0
RO R/W0C
0
0
568
April 08, 2008
Preliminary