LM3S3748 Datasheet, PDF (550/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
Bit/Field
2
1
0
Name
STALLED
TXRDY
RXRDY
Type
R/W0C
R/W1S
RO
Reset
0
0
0
Description
Endpoint Stalled
This bit is set when a STALL handshake is transmitted. The CPU should
clear this bit by writing a 0. This bit can only be cleared. Setting this bit
does nothing.
Transmit Packet Ready
The CPU writes a 1 to this bit after loading a data packet into the FIFO.
It is cleared automatically when the data packet has been transmitted.
An interrupt is also generated at this point.
Receive Packet Ready
This bit is set when a data packet has been received. An interrupt is
generated when this bit is set. The CPU clears this bit by setting the
RXRDYC bit.
550
April 08, 2008
Preliminary