LM3S3748 Datasheet, PDF (192/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Micro Direct Memory Access (μDMA)
9.2.4
The arbitration size can also be thought of as a burst size. It is the maximum number of items that
will be transferred at any one time in a burst. Here, the term arbitration refers to determination of
DMA channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus,
the processor always takes priority. Furthermore, the μDMA controller will be held off whenever the
processor needs to perform a bus transaction on the same bus, even in the middle of a burst transfer.
Request Types
The μDMA controller responds to two types of requests from a peripheral: single or burst. Each
peripheral may support either or both types of requests. A single request means that the peripheral
is ready to transfer one item, while a burst request means that the peripheral is ready to transfer
multiple items.
The μDMA controller responds differently depending on whether the peripheral is making a single
request or a burst request. If both are asserted and the μDMA channel has been set up for a burst
transfer, then the burst request takes precedence. See Table 9-2 on page 192, which shows how
each peripheral supports the two request types.
Table 9-2. Request Type Support
Peripheral Single Request Signal Burst Request Signal
USB TX None
FIFO TXRDY
USB RX None
FIFO RXRDY
UART TX TX FIFO Not Full
TX FIFO Level (configurable)
UART RX RX FIFO Not Empty RX FIFO Level (configurable)
SSI TX TX FIFO Not Full
TX FIFO Level (fixed at 4)
SSI RX RX FIFO Not Empty RX FIFO Level (fixed at 4)
9.2.4.1
9.2.4.2
9.2.5
Single Request
When a single request is detected, and not a burst request, the μDMA controller will transfer one
item, and then stop and wait for another request.
Burst Request
When a burst request is detected, the μDMA controller will transfer the number of items that is the
lesser of the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration
size should be the same as the number of data items that the peripheral can accomodate when
making a burst request. For example, the UART will generate a burst request based on the FIFO
trigger level. In this case, the arbitration size should be set to the amount of data that the FIFO can
transfer when the trigger level is reached.
It may be desirable to use only burst transfers and not allow single transfers. For example, perhaps
the nature of the data is such that it only makes sense when transferred together as a single unit
rather than one piece at a time. The single request can be disabled by using the DMA Channel
Useburst Set (DMAUSEBURSTSET) register. By setting the bit for a channel in this register, the
μDMA controller will only respond to burst requests for that channel.
Channel Configuration
The μDMA controller uses an area of system memory to store a set of channel control structures
in a table. The control table may have one or two entries for each DMA channel. Each entry in the
table structure contains source and destination pointers, transfer size, and transfer mode. The
control table can be located anywhere in system memory, but it must be contiguous and aligned on
a 1024-byte boundary.
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April 08, 2008
Preliminary