LM3S3748 Datasheet, PDF (66/753 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
6 System Control
6.1
6.1.1
6.1.2
6.1.2.1
6.1.2.2
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
Functional Description
The System Control module provides the following capabilities:
■ Device identification, see “Device Identification” on page 66
■ Local control, such as reset (see “Reset Control” on page 66), power (see “Power
Control” on page 69) and clock control (see “Clock Control” on page 69)
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 73
Device Identification
Seven read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC7 registers.
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
Reset Sources
The controller has six sources of reset:
1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 66.
2. Power-on reset (POR), see “Power-On Reset (POR)” on page 67.
3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 67.
4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 68.
5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 68.
6. MOSC failure
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
RST Pin Assertion
The external reset pin (RST) resets the controller. This resets the core and all the peripherals except
the JTAG TAP controller (see “JTAG Interface” on page 54). The external reset sequence is as
follows:
1. The external reset pin (RST) is asserted and then de-asserted.
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April 08, 2008
Preliminary