LM3S3748 Datasheet, PDF (191/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
9.2.1
9.2.2
9.2.3
Channel Assigments
μDMA channels 0-31 are assigned to peripherals according to the following table.
Note: Channels that are not listed in the table may be assigned to peripherals in the future.
However, they are currently available for software use.
Table 9-1. DMA Channel Assignments
DMA Channel Peripheral Assigned
0
USB Endpoint 1 Receive
1
USB Endpoint 1 Transmit
2
USB Endpoint 2 Receive
3
USB Endpoint 2 Transmit
4
USB Endpoint 3 Receive
5
USB Endpoint 3 Transmit
8
UART0 Receive
9
UART0 Transmit
10
SSI0 Receive
11
SSI0 Transmit
22
UART1 Receive
23
UART1 Transmit
24
SSI1 Receive
25
SSI1 Transmit
30
Dedicated for software use
Priority
The μDMA controller assigns priority to each channel based on the channel number and the priority
level bit for the channel. Channel number 0 has the highest priority and as the channel number
increases, the priority of a channel decreases. Each channel has a priority level bit to provide two
levels of priority: default priority and high priority. If the priority level bit is set, then that channel has
higher priority than all other channels at default priority. If multiple channels are set for high priority,
then the channel number is used to determine relative priority among all the high priority channels.
The priority bit for a channel can be set using the DMA Channel Priority Set (DMAPRIOSET)
register, and cleared with the DMA Channel Priority Clear (DMAPRIOCLR) register.
Arbitration Size
When a μDMA channel requests a transfer, the μDMA controller arbitrates between all the channels
making a request and services the DMA channel with the highest priority. Once a transfer begins,
it continues for a selectable number of transfers before rearbitrating among the requesting channels
again. The arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers.
After the μDMA controller transfers the number of items specified by the arbitration size, it then
checks among all the channels making a request and services the channel with the highest priority.
If a lower priority DMA channel uses a large arbitration size, the latency for higher priority channels
will be increased because the μDMA controller will complete the lower priority burst before checking
for higher priority requests. Therefore, lower priority channels should not use a large arbitration size
for best response on high priority channels.
April 08, 2008
191
Preliminary