LM3S3748 Datasheet, PDF (581/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Register 88: USB External Power Control (USBEPC), offset 0x400
Host
USBEPC is instantiated in a USB unit in a wrapper around the USB controller/PHY IP. This 32-bit
register specifies the function of the two-pin external power interface (USB0EPEN and USB0PFLT).
The assertion of the power fault input may generate an automatic action, as controlled by the
hardware configuration registers. The automatic action is necessary since the fault condition may
require a response faster than one provided by firmware.
USB External Power Control (USBEPC)
Base 0x4005.0000
Offset 0x400
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
Type RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
15
14
13
12
11
10
reserved
Type RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
25
24
23
22
21
20
19
18
17
16
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
9
8
PFLTACT
R/W
R/W
0
0
7
6
5
4
3
2
reserved PFLTAEN PFLTSEN PFLTEN reserved EPENDE
RO
R/W
R/W
R/W
RO
R/W
0
0
0
0
0
0
1
0
EPEN
R/W
R/W
0
0
Bit/Field
31:10
9:8
Name
reserved
PFLTACT
Type
RO
R/W
Reset
0x00
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power Fault Action
Specifies how the USB0EPEN signal is changed when detecting a USB
power fault.
Value Description
0x0 Unchanged
USB0EPEN is controlled by the combination of the EPEN and
EPENDE bits.
0x1 Tristate
USB0EPEN is undriven (tristate).
0x2 Low
USB0EPEN driven Low.
0x3 High
USB0EPEN driven High.
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
581
Preliminary