LM3S3748 Datasheet, PDF (230/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Micro Direct Memory Access (μDMA)
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028
Each bit of the DMAENASET register represents the corresponding DMA channel. Writing a 1
enables the DMA channel. Reading the register returns the enable status of the channels. If a
channel is enabled but the request mask is set (DMAREQMASKSET), then the channel can be
used for software-initiated transfers.
DMAENASET Reads
DMA Channel Enable Set (DMAENASET)
Base 0x400F.F000
Offset 0x028
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SET[n]
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SET[n]
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
SET[n]
Type
R
Reset
0x00
Description
Channel [n] Enable Set
Returns the enable status of the channels.
Value Description
0 Disabled
1 Enabled
DMAENASET Writes
DMA Channel Enable Set (DMAENASET)
Base 0x400F.F000
Offset 0x028
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CHENSET[n]
Type W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CHENSET[n]
Type W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
230
April 08, 2008
Preliminary