LM3S3748 Datasheet, PDF (391/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
14.2.7
14.2.8
■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 413).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 410) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 412).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 414).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data (or by reading the holding register), or when a 1 is
written to the corresponding bit in the UARTICR register.
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 406). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
DMA Operation
The UART provides an interface connected to the μDMA controller. The DMA operation of the UART
is enabled through the UART DMA Control (UARTDMACTL) register. When DMA operation is
enabled, the UART will assert a DMA request on the receive or transmit channel when the associated
FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever
there is any data in the receive FIFO. A burst transfer request is asserted whenever the amount of
data in the receive FIFO is at or above the FIFO trigger level. For the transmit channel, a single
transfer request is asserted whenever there is at least one empty location in the transmit FIFO. The
burst request is asserted whenever the transmit FIFO contains fewer characters than the FIFO
trigger level. The single and burst DMA transfer requests are handled automatically by the μDMA
controller depending how the DMA channel is configured.
To enable DMA operation for the receive channel, the RXDMAE bit of the DMA Control
(UARTDMACTL) register should be set. To enable DMA operation for the transmit channel, the
TXDMAE bit of UARTDMACTL should be set. The UART can also be configured to stop using DMA
for the receive channel if a receive error occurs. If the DMAERR bit of UARTDMACR is set, then
when a receive error occurs, the DMA receive requests will be automatically disabled. This error
condition can be cleared by clearing the UART error interrupt.
If DMA is enabled, then the μDMA controller will trigger an interrupt when a transfer is complete.
The interrupt will occur on the UART interrupt vector. Therefore, if interrupts are used for UART
April 08, 2008
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Preliminary