LM3S3748 Datasheet, PDF (16/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 320
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 321
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 323
GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 324
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 325
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 326
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 327
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 328
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 329
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 330
Watchdog Timer ........................................................................................................................... 331
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 334
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 335
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 336
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 337
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 338
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 339
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 340
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 341
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 342
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 343
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 344
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 345
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 346
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 347
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 348
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 349
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 350
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 351
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 352
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 353
Analog-to-Digital Converter (ADC) ............................................................................................. 354
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 362
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 363
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 364
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 365
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 366
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 367
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 370
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 371
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 372
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 373
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 374
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 376
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 379
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 379
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 379
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 379
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April 08, 2008
Preliminary