LM3S3748 Datasheet, PDF (610/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Pulse Width Modulator (PWM)
7. Set the pulse width of the PWM0 pin for a 25% duty cycle.
■ Write the PWM0CMPA register with a value of 0x0000.012B.
8. Set the pulse width of the PWM1 pin for a 75% duty cycle.
■ Write the PWM0CMPB register with a value of 0x0000.0063.
9. Start the timers in PWM generator 0.
■ Write the PWM0CTL register with a value of 0x0000.0001.
10. Enable PWM outputs.
■ Write the PWMENABLE register with a value of 0x0000.0003.
19.4
Register Map
Table 19-1 on page 610 lists the PWM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the PWM base address of 0x4002.8000.
Table 19-1. PWM Register Map
Offset Name
Type
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
0x060
PWMCTL
PWMSYNC
PWMENABLE
PWMINVERT
PWMFAULT
PWMINTEN
PWMRIS
PWMISC
PWMSTATUS
PWMFAULTVAL
PWM0CTL
PWM0INTEN
PWM0RIS
PWM0ISC
PWM0LOAD
PWM0COUNT
PWM0CMPA
PWM0CMPB
PWM0GENA
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W1C
RO
R/W
R/W
R/W
RO
R/W1C
R/W
RO
R/W
R/W
R/W
Reset
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Description
PWM Master Control
PWM Time Base Sync
PWM Output Enable
PWM Output Inversion
PWM Output Fault
PWM Interrupt Enable
PWM Raw Interrupt Status
PWM Interrupt Status and Clear
PWM Status
PWM Fault Condition Value
PWM0 Control
PWM0 Interrupt and Trigger Enable
PWM0 Raw Interrupt Status
PWM0 Interrupt Status and Clear
PWM0 Load
PWM0 Counter
PWM0 Compare A
PWM0 Compare B
PWM0 Generator A Control
See
page
613
614
615
617
618
620
622
624
626
627
629
634
636
637
638
639
640
641
642
610
April 08, 2008
Preliminary