LM3S3748 Datasheet, PDF (728/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Register Quick Reference
31
30
29
28
27
26
15
14
13
12
11
10
FMPRE3, type R/W, offset 0x20C, reset 0x0000.0000
FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF
FMPPE2, type R/W, offset 0x408, reset 0x0000.0000
FMPPE3, type R/W, offset 0x40C, reset 0x0000.0000
Micro Direct Memory Access (μDMA)
μDMA Channel Control Structure
Base n/a
DMASRCENDP, type R/W, offset 0x000, reset -
DMADSTENDP, type R/W, offset 0x004, reset -
DMACHCTL, type R/W, offset 0x008, reset -
DSTINC
ARBSIZE
DSTSIZE
SRCINC
Micro Direct Memory Access (μDMA)
μDMA Registers
Base 0x400F.F000
DMASTAT, type RO, offset 0x000, reset 0x001F.0000
DMACFG, type WO, offset 0x004, reset -
25
24
23
22
21
9
8
7
6
5
READ_ENABLE
READ_ENABLE
PROG_ENABLE
PROG_ENABLE
PROG_ENABLE
PROG_ENABLE
PROG_ENABLE
PROG_ENABLE
ADDR
ADDR
ADDR
ADDR
SRCSIZE
XFERSIZE
STATE
DMACTLBASE, type R/W, offset 0x008, reset 0x0000.0000
ADDR
DMAALTBASE, type RO, offset 0x00C, reset 0x0000.0200
DMAWAITSTAT, type RO, offset 0x010, reset 0x0000.0000
DMASWREQ, type WO, offset 0x014, reset -
DMAUSEBURSTSET, type RO, offset 0x018, reset 0x0000.0000
DMAUSEBURSTSET, type WO, offset 0x018, reset 0x0000.0000
ADDR
ADDR
ADDR
WAITREQ[n]
WAITREQ[n]
SWREQ[n]
SWREQ[n]
SET[n]
SET[n]
SET[n]
SET[n]
20
19
18
17
16
4
3
2
1
0
NXTUSEBURST
ARBSIZE
XFERMODE
DMACHANS
MASTEN
MASTEN
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April 08, 2008
Preliminary