LM3S3748 Datasheet, PDF (145/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
When the hibernation module has no externally applied voltage and detects a change to either
VDD or VBAT, it resets all hibernation module registers to the value in Table 7-1 on page 145.
■ Reset During Hibernation Module Disable
When the module has either not been enabled or has been disabled by software, the reset is
passed through to the Hibernation module circuitry and the internal state of the module is reset.
■ Reset While HIB Module is in Hibernation Mode
While in Hibernation mode, or while transitioning from Hibernation mode to run mode (leaving
the power cut), the reset generated by the POR circuitry of the device is suppressed, and the
state of the Hibernation module's registers is unaffected.
■ Reset While HIB Module is in Normal Mode
While in normal mode (not hibernating), any reset is suppressed, and the content/state of the
control and data registers is unaffected.
Software must initialize any control or data registers in this condition. Therefore, software is the
only mechanism to enable or disable the oscillator and real-time clock operation, or to clear
contents of the data memory. The only state that must be cleared by a reset operation while not
in Hibernation mode is any state that prevents software from managing the interface.
7.4 Register Map
Table 7-1 on page 145 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000.
Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of t_{HIB_REG_WRITE} between write
accesses. See “Register Access Timing” on page 138.
Table 7-1. Hibernation Module Register Map
Offset Name
Type
Reset
Description
0x000 HIBRTCC
0x004 HIBRTCM0
0x008 HIBRTCM1
0x00C HIBRTCLD
0x010 HIBCTL
0x014 HIBIM
0x018 HIBRIS
0x01C HIBMIS
0x020 HIBIC
0x024 HIBRTCT
0x030-
0x12C
HIBDATA
RO
R/W
R/W
R/W
R/W
R/W
RO
RO
R/W1C
R/W
R/W
0x0000.0000
0xFFFF.FFFF
0xFFFF.FFFF
0xFFFF.FFFF
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.7FFF
0x0000.0000
Hibernation RTC Counter
Hibernation RTC Match 0
Hibernation RTC Match 1
Hibernation RTC Load
Hibernation Control
Hibernation Interrupt Mask
Hibernation Raw Interrupt Status
Hibernation Masked Interrupt Status
Hibernation Interrupt Clear
Hibernation RTC Trim
Hibernation Data
See
page
147
148
149
150
151
154
155
156
157
158
159
April 08, 2008
145
Preliminary