LM3S3748 Datasheet, PDF (416/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Register 14: UART DMA Control (UARTDMACTL), offset 0x048
The UARTDMACTL register is the DMA control register.
UART DMA Control (UARTDMACTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x048
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DMAERR TXDMAE RXDMAE
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
1
0
Name
reserved
DMAERR
TXDMAE
RXDMAE
Type
RO
R/W
R/W
R/W
Reset
0x00
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
DMA on Error
If this bit is set to 1, DMA receive requests are automatically disabled
when a receive error occurs.
Transmit DMA Enable
If this bit is set to 1, DMA for the transmit FIFO is enabled.
Receive DMA Enable
If this bit is set to 1, DMA for the receive FIFO is enabled.
416
April 08, 2008
Preliminary