LM3S3748 Datasheet, PDF (114/753 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Register 24: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31
30
29
28
27
26
25
24
23
22
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
reserved
MAXADCSPD reserved HIB
Type RO
RO
RO
RO
RO
RO
R/W
R/W
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
21
20
PWM
RO
R/W
0
0
5
4
reserved
RO
RO
0
0
19
18
17
reserved
RO
RO
RO
0
0
0
16
ADC
R/W
0
3
WDT
R/W
0
2
1
0
reserved
RO
RO
RO
0
0
0
Bit/Field
31:21
20
19:17
16
15:10
Name
reserved
PWM
reserved
ADC
reserved
Type
RO
R/W
RO
R/W
RO
Reset
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Clock Gating Control. This bit controls the clock gating for the
PWM module. If set, the unit receives a clock and functions. Otherwise,
the unit is unclocked and disabled. If the unit is unclocked, a read or
write to the unit generates a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC0 Clock Gating Control. This bit controls the clock gating for general
SAR ADC module 0. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled. If the unit is unclocked,
a read or write to the unit generates a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
114
April 08, 2008
Preliminary