LM3S3748 Datasheet, PDF (651/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Register 63: PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074
Register 64: PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4
Register 65: PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4
Register 66: PWM3 Fault Source 0 (PWM3FLTSRC0), offset 0x134
This register is instantiated in each PWM generator, and it specifies which fault pin outputs are used
to signal a fault condition.
If the FLTSRC bit in the PWMnCTL register (see page 629) is clear, only the Fault0 bit affects the
fault condition generated. Otherwise, all other bits affect the fault condition generated.
PWM0 Fault Source 0 (PWM0FLTSRC0)
Base 0x4002.8000
Offset 0x074
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FAULT3 FAULT2 FAULT1 FAULT0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
2
1
Name
reserved
FAULT3
FAULT2
FAULT1
Type
RO
R/W
R/W
R/W
Reset
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault3
The same function as Fault0, except applied for the FAULT3 input.
Note: The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Fault2
The same function as Fault0, except applied for the FAULT2 input.
Note: The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Fault1
The same function as Fault0, except applied for the FAULT1 input.
Note: The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
April 08, 2008
651
Preliminary