LM3S3748 Datasheet, PDF (506/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
software to write larger amounts of data to an endpoint in a single operation than can be transferred
in a single USB operation.
To simplify this case, the Stellaris^® USB controller includes a packet-splitting feature that allows
larger data packets to be written to bulk transmit endpoints, which are then split into packets of an
appropriate size for transfer across the USB bus. With this option, the USBTXMAXPn register uses
the bottom 11 bits to define the payload for each individual transfer, while the top 5 bits define a
multiplier. The application software can then write data packets of size multiplier × payload to the
FIFO, which the USB controller then splits into individual packets of the stated payload for
transmission over the USB bus. From the application software’s point-of-view, the resulting operation
does not differ from the transmission of a single USB packet except in the size of the packet written.
Note:
Packet-splitting can only be used with bulk endpoints and, in accordance with the USB
specification, the payload must be 8, 16, 32, or 64. The payload recorded in the
USBTXMAXPn register must also match the wMaxPacketSize field of the Standard
Endpoint Descriptor for the endpoint (see chapter 9 of the USB specification). The associated
FIFO must also be large enough to accommodate the data packet prior to being split.
17.2.1.3 OUT Transactions as a Device
When in device mode, OUT transactions are handled through the USB controller receive FIFOs.
The sizes of the receive FIFOs for endpoints 1-3 are determined by the USBRXFIFOADD register.
The maximum amount of data received by an endpoint in any packet is determined by the value
written to the USBRXMAXPn register for that endpoint. When double-packet buffering is enabled,
two data packets can be buffered in the FIFO. When double-packet buffering is disabled, only one
packet can be buffered even if the packet is less than half the FIFO size. The Stellaris^® USB controller
also supports a special mode for bulk endpoints that allows automatic splitting of a larger FIFO into
multiple maximum packet size transfers.
Note: In all cases, the maximum packet size must not exceed the FIFO size.
Single-Packet Buffering
If the size of the receive endpoint FIFO is less than twice the maximum packet size for an endpoint,
only one data packet can be buffered in the FIFO and single-packet buffering is required. When a
packet is received and placed in the receive FIFO, the RXRDY and FULL bits in the USBRXCSRLn
register are set and the appropriate receive endpoint is signaled, indicating that a packet can now
be unloaded from the FIFO. After the packet has been unloaded, the RXRDY bit needs to be cleared
in order to allow further packets to be received. This action also generates the acknowledge signaling
to the host controller. If the AUTOCL bit in the USBRXCSRHn register is set and a maximum-sized
packet is unloaded from the FIFO, the RXRDY and FULL bits are cleared automatically. For packet
sizes less than the maximum, RXRDY must be cleared manually.
Double-Packet Buffering
If the size of the receive endpoint FIFO is at least twice the maximum packet size for the endpoint,
two data packets can be buffered and double-packet buffering can be used. When the first packet
is received and loaded into the receive FIFO, the RXRDY bit in the USBRXCSRLn register is set
and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now be
unloaded from the FIFO.
Note: The FULL bit in USBRXCSRLn is not set when the first packet is received. It is only set if
a second packet is received and loaded into the receive FIFO.
After each packet has been unloaded, the RXRDY bit needs to be cleared in order to allow further
packets to be received. If the AUTOCL bit in the USBRXCSRHn register is set and a maximum-sized
506
April 08, 2008
Preliminary