LM3S3748 Datasheet, PDF (567/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Bit/Field
7
6
5
4
3
Name
AUTOCL
AUTORQ
DMAEN
PIDERR
DMAMOD
Type
R/W
R/W
R/W
RO
R/W
Reset
0
0
0
0
0
Description
Auto Clear
If the CPU sets this bit, then the RXRDY bit is automatically cleared when
a packet of USBRXMAXPn bytes has been unloaded from the receive
FIFO. When packets of less than the maximum packet size are unloaded,
RXRDY must be cleared manually. When using a DMA to unload the
receive FIFO, data is read from the receive FIFO in 4 byte chunks
regardless of the RxMaxP. Therefore, the RXRDY bit is cleared as follows.
Remainder (RxMaxP/4)
Value Description
0 RXMaxP = 64 bytes
1 RXMaxP = 61 bytes
2 RXMaxP = 62 bytes
3 RXMaxP = 63 bytes
Actual Bytes Read
Value Description
0 RXMAXP
1 RXMAXP+3
2 RXMAXP+2
3 RXMAXP+1
Packet Sizes that will clear RXRDY
Value Description
0 RXMAXP, RXMAXP-1, RXMAXP-2, RXMAXP-3
1 RXMAXP
2 RXMAXP, RXMAXP-1
3 RXMAXP, RXMAXP-1, RXMAXP-2
Note: This bit should not be set for high-bandwidth isochronous
endpoints.
Auto Request
If the CPU sets this bit, the ReqPkt bit is automatically set when the
RXRDY bit is cleared.
Note: This bit is automatically cleared when a short packet is
received.
DMA Request Enable
The CPU sets this bit to enable the DMA request for the receive endpoint.
PID Error
For ISO transactions, the core sets this bit to indicate a PID error in the
received packet. This bit is ignored in bulk or interrupt transactions.
DMA Request Mode
The CPU sets this bit to select DMA Request Mode 1 and clears it to
select DMA Request Mode 0.
April 08, 2008
567
Preliminary