LM3S3748 Datasheet, PDF (549/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Bit/Field
1
0
Name
TXRDY
RXRDY
Type
R/W1S
R/W0C
Reset
0
0
Description
Transmit Packet Ready
The CPU sets this bit after loading a data packet into the FIFO. It is
cleared automatically when a data packet has been transmitted. An
interrupt is also generated at this point.
Receive Packet Ready
This bit is set when a data packet has been received. An interrupt is
generated when this bit is set. The CPU should clear this bit, by writing
a 0 when the packet has been read from the FIFO. This acknowledges
that data has been read from the FIFO.
USBCSRL0 Device Mode
USB Control and Status Endpoint 0 Low (USBCSRL0)
Base 0x4005.0000
Offset 0x102
Type W1C, reset 0x00
7
6
5
4
3
2
1
0
SETENDC RXRDYC STALL SETEND DATAEND STALLED TXRDY RXRDY
Type W1C W1C W1C
RO
W1C R/W0C R/W1S RO
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
6
5
4
3
Name
SETENDC
RXRDYC
STALL
SETEND
DATAEND
Type
W1C
W1C
W1C
RO
W1C
Reset
0
0
0
0
0
Description
Setup End Clear
The CPU writes a 1 to this bit to clear the SETEND bit.
RXRDY Clear
The CPU writes a 1 to this bit to clear the RXRDY bit.
Send Stall
The CPU writes a 1 to this bit to terminate the current transaction. The
STALL handshake is transmitted, and then this bit is cleared
automatically.
Setup End
This bit is set when a control transaction ends before the DataEnd bit
has been set. An interrupt is generated and the FIFO flushed at this
time. The bit is cleared by the CPU writing a 1 to the SETENDC bit.
Data End
The CPU sets this bit:
■ When setting TXRDY for the last data packet
■ When clearing RXRDY after unloading the last data packet
■ When setting TXRDY for a zero-length data packet
It is cleared automatically.
April 08, 2008
549
Preliminary