LM3S3748 Datasheet, PDF (655/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Register 75: PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804
Register 76: PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884
Register 77: PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904
Register 78: PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984
This register provides status regarding the fault condition inputs. If the PWMnCTL register LATCH
bit is cleared, the contents of the PWMnFLTSTAT0 provide the current state of the FAULTn inputs.
If the LATCH bit is set, the contents of the PWMnFLTSTAT0 provide a latched version of the FAULTn
inputs. The register bits are cleared by writing a one to a set bit.
The FAULTn inputs are recorded after their sense is adjusted in the generator.
PWM0 Fault Status 0 (PWM0FLTSTAT0)
Base 0x4002.8000
Offset 0x804
Type -, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FAULT3 FAULT2 FAULT1 FAULT0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
-
-
-
-
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
2
1
Name
reserved
FAULT3
FAULT2
FAULT1
Type
RO
-
-
-
Reset
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Input 3
The same function as FAULT0, except applied for the FAULT3 input.
Fault Input 2
The same function as FAULT0, except applied for the FAULT2 input.
Fault Input 1
The same function as FAULT0, except applied for the FAULT1 input.
April 08, 2008
655
Preliminary