LM3S3748 Datasheet, PDF (563/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Register 62: USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1),
offset 0x116
Register 63: USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2),
offset 0x126
Register 64: USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3),
offset 0x136
Host
USBRXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected receive endpoint.
Device
USBRXCSRLn Host Mode
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1)
Base 0x4005.0000
Offset 0x116
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
CLRDT STALLED REQPKT FLUSH ^{DATAERR /} ERROR FULL RXRDY
NAKTO
Type W1S R/W0C R/W
Reset
0
0
0
W1S R/W0C R/W0C RO R/W0C
0
0
0
0
0
Bit/Field
7
6
5
4
Name
CLRDT
STALLED
REQPKT
FLUSH
Type
W1S
R/W0C
R/W
W1S
Reset
0
0
0
0
Description
Clear Data Toggle
The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
Endpoint Stalled
When a STALL handshake is received, this bit is set and an interrupt is
generated. The CPU should clear this bit.
Request Packet
The CPU writes a 1 to this bit to request an IN transaction. It is cleared
when RXRDY is set.
Flush FIFO
The CPU writes a 1 to this bit to flush the next packet to be read from
the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit
is cleared.
Note:
FLUSH should only be used when RXRDY is set. At other times,
it may cause data to be corrupted. Also note that, if the FIFO
is double-buffered, FLUSH may need to be set twice to
completely clear the FIFO.
April 08, 2008
563
Preliminary