LM3S3748 Datasheet, PDF (558/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
Bit/Field
5
4
3
2
1
0
Name
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
Type
R/W0C
R/W
W1C
R/W0C
R/W0C
R/W1S
Reset
0
0
0
0
0
0
Description
Endpoint Stalled
This bit is set when a STALL handshake is transmitted. The FIFO is
flushed and the TXRDY bit is cleared. The CPU should clear this bit.
Send Stall
The CPU writes a 1 to this bit to issue a STALL handshake to an IN
token. The CPU clears this bit to terminate the stall condition.
Note: This bit has no effect in isochronous transfers.
Flush FIFO
The CPU writes a 1 to this bit to flush the latest packet from the endpoint
transmit FIFO. The FIFO pointer is reset, the TXRDY bit is cleared, and
an interrupt is generated. This bit may be set simultaneously with TXRDY
to abort the packet that is currently being loaded into the FIFO.
Note:
FLUSH should only be used when TXRDY is set. At other times,
it may cause data to be corrupted. Also note that, if the FIFO
is double-buffered, FLUSH may need to be set twice to
completely clear the FIFO.
Underrun
The USB controller sets this bit if an IN token is received when TXRDY
is not set. The CPU should clear this bit.
FIFO Not Empty
The USB controller sets this bit when there is at least 1 packet in the
transmit FIFO.
Transmit Packet Ready
The CPU sets this bit after loading a data packet into the FIFO. It is
cleared automatically when a data packet has been transmitted. An
interrupt is generated at this point. TXRDY is also automatically cleared
prior to loading a second packet into a double-buffered FIFO.
558
April 08, 2008
Preliminary