LM3S3748 Datasheet, PDF (250/753 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Input/Outputs (GPIOs)
10
10.1
General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of eight physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, and Port H). The GPIO module
supports 3-61 programmable input/output pins, depending on the peripherals being used.
The GPIO module has the following features:
■ Two means of port access: either high speed (for single-cyle writes), or legacy for
backwards-compatibility with existing code
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ 5-V-tolerant input/outputs
■ Bit masking in both read and write operations through address lines
■ Pins configured as digital inputs are Schmitt-triggered.
■ Programmable control for GPIO pad configuration:
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured
with an 18-mA pad drive for high-current applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the four JTAG/SWD pins (PC[3:0]). The
JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1
and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins
back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block(see Figure
10-1 on page 251 and Figure 10-2 on page 252). The LM3S3748 microcontroller contains eight ports
and thus eight of these physical GPIO blocks.
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April 08, 2008
Preliminary