LM3S3748 Datasheet, PDF (586/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
Register 91: USB External Power Control Interrupt Status and Clear
(USBEPCISC), offset 0x40C
Host
USBEPCISC is instantiated in a USB unit in a wrapper around the USB controller/PHY IP. This
32-bit register specifies the masked interrupt status of the two-pin external power interface. It also
provides a method to clear the interrupt state.
Device
USB External Power Control Interrupt Status and Clear (USBEPCISC)
Base 0x4005.0000
Offset 0x40C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PF
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
PF
Type
RO
R/W1C
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Power Fault Interrupt Status and Clear
Specifies whether a detected power fault has generated an interrupt.
Value Description
0 No Interrupt
The hardware has not generated an interrupt for a detected
power fault condition.
1 Interrupt
The hardware has generated an interrupt for a detected power
fault condition.
Writing a 1 to this bit clears it and the USBEPCRIS PF bit. This bit is
set if the USBEPCRIS PF bit is set (by hardware) and the USBEPCIM
PF bit is set.
586
April 08, 2008
Preliminary