LM3S3748 Datasheet, PDF (499/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Register 13: I²C Slave Interrupt Mask (I2CSIMR), offset 0x00C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
STOPIM STARTIM DATAIM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
1
0
Name
reserved
STOPIM
STARTIM
DATAIM
Type
RO
RO
RO
R/W
Reset
0x00
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Stop Condition Interrupt Mask
This bit controls whether the raw interrupt for detection of a stop condition
on the I²C bus is promoted to a controller interrupt. If set, the interrupt
is not masked and the interrupt is promoted; otherwise, the interrupt is
masked.
Start Condition Interrupt Mask
This bit controls whether the raw interrupt for detection of a start condition
on the I²C bus is promoted to a controller interrupt. If set, the interrupt
is not masked and the interrupt is promoted; otherwise, the interrupt is
masked.
Data Interrupt Mask
This bit controls whether the raw interrupt for data received and data
requested is promoted to a controller interrupt. If set, the interrupt is not
masked and the interrupt is promoted; otherwise, the interrupt is masked.
April 08, 2008
499
Preliminary