LM3S3748 Datasheet, PDF (536/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
Register 17: USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062
Register 18: USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063
Host
These 8-bit registers allow the selected TX/RX endpoint FIFOs to be dynamically sized. USBEPIDX
is used to configure each transmit endpoint's FIFO size.
Device
USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ)
Base 0x4005.0000
Offset 0x062
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
reserved
DPB
SIZE
Type RO
RO
RO
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit/Field
7:5
4
3:0
Name
reserved
DPB
SIZE
Type
RO
R/W
R/W
Reset
0x00
0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Double Packet Buffer Support
Defines whether double-packet buffering is supported. When 1,
double-packet buffering is supported. When 0, only single-packet
buffering is supported.
Max Packet Size
Maximum packet size to be allowed for (before any splitting within the
FIFO of bulk/high-bandwidth packets prior to transmission.
If DPB = 0, the FIFO also is this size; if DPB = 1, the FIFO is twice this
size.
Value Packet Size (Bytes)
0x0 8
0x1 16
0x2 32
0x3 64
0x4 128
0x5 256
0x6 512
0x7 1024
0x8 2048
0x9-0xF Reserved
536
April 08, 2008
Preliminary