LM3S3748 Datasheet, PDF (520/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
Bit/Field
7
6
5:4
3
2
1
0
Name
ISOUP
SOFTCONN
reserved
RESET
RESUME
SUSPEND
PWRDNPHY
Type
R/W
R/W
RO
RO
R/W
RO
R/W
Reset
0
0
0x2
0
0
0
0
Description
ISO Update
When set by the CPU, the USB controller waits for an SOF token from
the time TXRDY is set before sending the packet. If an IN token is
received before an SOF token, then a zero-length data packet is sent.
Note: Only valid for isochronous transfers.
Soft Connect/Disconnect
The USB D+/D- lines are enabled when this bit is set by the CPU, and
tri-stated when this bit is cleared by the CPU.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Reset
This bit is set when Reset signaling is present on the bus.
Resume Signaling
Set by the CPU to generate Resume signaling when the device is in
Suspend mode. The CPU should clear this bit after 10 ms (a maximum
of 15 ms) to end Resume signaling.
Suspend Mode
This bit is set on entry into Suspend mode. It is cleared when the CPU
reads the interrupt register or sets the RESUME bit above.
Power Down PHY
Set by the CPU to power down the internal USB PHY.
520
April 08, 2008
Preliminary